Real Time
A time which always increments without stopping or resetting.
A time which always increments without stopping or resetting.
Sunday, August 11, 2013
HDLC ( High level Data Link Control)
HDLC ( High level Data Link Control)
High level Data Link Control for synchronous communication between primary (master) and secondary (slave) as per standard defined. It is a bit-oriented protocol.
High level Data Link Control for synchronous communication between primary (master) and secondary (slave) as per standard defined. It is a bit-oriented protocol.
Protocol
Protocol
A way of transmitting messages on a network by using a software for adding the additional bits like staring bits, headers, addresses of source and destination, error control its and ending bits. Each layer or sub layer uses its protocol before a message transmits on a network.
A way of transmitting messages on a network by using a software for adding the additional bits like staring bits, headers, addresses of source and destination, error control its and ending bits. Each layer or sub layer uses its protocol before a message transmits on a network.
RS232 Port
RS232 Port
A standard for UART transmission and reception in which TxD and RxD are at different voltage levels and handshaking signals, CTS,RTS, DTR, DCD and RT are at the TTL levels.
A standard for UART transmission and reception in which TxD and RxD are at different voltage levels and handshaking signals, CTS,RTS, DTR, DCD and RT are at the TTL levels.
RxD
RxD
A line used for reception of UART serial bits. The 0 and 1 signals are at levels similar that for TxD line.
A line used for reception of UART serial bits. The 0 and 1 signals are at levels similar that for TxD line.
TxD
TxD
A line used for transmission of UART serial bits. The 0 and 1 signals are at RS232C voltage levels when RS232C COM port is used, or at the TTL levels in micro controllers.
A line used for transmission of UART serial bits. The 0 and 1 signals are at RS232C voltage levels when RS232C COM port is used, or at the TTL levels in micro controllers.
UART
UART
A standard asynchronous serial input and out port for serial bits. UART ( in micro controllers ) usually sends a byte in 10-bits format or 11-bits format. The 10-bits format is when a start bit precedes the 8-bit message and a stop bit succeeds the message. An 11- bit format is when a serial bit also precedes the stop bit.
A standard asynchronous serial input and out port for serial bits. UART ( in micro controllers ) usually sends a byte in 10-bits format or 11-bits format. The 10-bits format is when a start bit precedes the 8-bit message and a stop bit succeeds the message. An 11- bit format is when a serial bit also precedes the stop bit.
Device Decoder
Device Decoder
A circuit to take the address bus signals as the input and generate a chip select signal, CS, for the port address selection.
A circuit to take the address bus signals as the input and generate a chip select signal, CS, for the port address selection.
Full Duplex
Full Duplex
A serial port having two distinct I/O lines.
Example:- a modem - message flows both ways at an instance.
A serial port having two distinct I/O lines.
Example:- a modem - message flows both ways at an instance.
Half Duplex
Half Duplex
A serial port having one common I/O line.
Example:- A telephone line - message flows one way at an instance.
A serial port having one common I/O line.
Example:- A telephone line - message flows one way at an instance.
I/o Port
I/o Port
A port for input or output operation at an instant. Handshake input and handshake output ports are also known as I/O ports.
Example:- A printer is said to connect to an I/O port.
A port for input or output operation at an instant. Handshake input and handshake output ports are also known as I/O ports.
Example:- A printer is said to connect to an I/O port.
Status Register
Status Register
A register for bits, which reflects the current status at the port buffer. It is a read operation only. The bit may or may not auto-reset on device servicing.
A register for bits, which reflects the current status at the port buffer. It is a read operation only. The bit may or may not auto-reset on device servicing.
Control Register
Control Register
A register for bits, which controls the actions of a device. It is for a write operation only.
A register for bits, which controls the actions of a device. It is for a write operation only.
Handshaking Signals
Handshaking Signals
The signals before storing the bits at the port buffer or before accepting the bits from the port buffer.
The signals before storing the bits at the port buffer or before accepting the bits from the port buffer.
DMA (Direct Memory Access)
DMA (Direct Memory Access)
A direct memory access by a controller internal or external. DMA operations facilitating the peripherals and devices of the system to obtain access to the system directly without processor controlling the transfer of the bytes in a memory block.
A direct memory access by a controller internal or external. DMA operations facilitating the peripherals and devices of the system to obtain access to the system directly without processor controlling the transfer of the bytes in a memory block.
Interface Circuit
Interface Circuit
A circuit consisting of the latches, decoders, multiplexers, demultiplexers.
A circuit consisting of the latches, decoders, multiplexers, demultiplexers.
Timing Diagram
Timing Diagram
A diagram that reflects the relative time intervals of the signals on he external buses with respect to the processor clock pulses.
A diagram that reflects the relative time intervals of the signals on he external buses with respect to the processor clock pulses.
Device Address
Device Address
A device address used by processor to access its set of registers. At each address there may be one or more device registers.
A device address used by processor to access its set of registers. At each address there may be one or more device registers.
Device
Device
A physical or virtual unit that has three sets of registers- Data registers , control registers and status registers and that the processor addresses these like a memory.
or
A unit that connects to the processing unit through the ports. It has fixed pre-assigned port address(device addresses) according to its interfacing circuit.
A physical or virtual unit that has three sets of registers- Data registers , control registers and status registers and that the processor addresses these like a memory.
or
A unit that connects to the processing unit through the ports. It has fixed pre-assigned port address(device addresses) according to its interfacing circuit.
Memory Map
Memory Map
A memory addresses allocation table such that the map reflects the available memory addresses for various uses of the processor. A memory map defines the addresses of the ROMs AND RAMs of the systems.
A memory addresses allocation table such that the map reflects the available memory addresses for various uses of the processor. A memory map defines the addresses of the ROMs AND RAMs of the systems.
Boot Back Flash
Boot Back Flash
A flash with a few sectors similar to an OTP device , to enable storage of boost up program and initial data.
A flash with a few sectors similar to an OTP device , to enable storage of boost up program and initial data.
Flash
Flash
A type of memory a sector of bytes that is erasable many times ( maximum 10000 times) in a flash at the same instance in a single cycle. Each erased byte is then programmable by the write instruction of a program as well as by a device programmer.
A type of memory a sector of bytes that is erasable many times ( maximum 10000 times) in a flash at the same instance in a single cycle. Each erased byte is then programmable by the write instruction of a program as well as by a device programmer.
EEPROM
EEPROM
A type of memory each byte of which is erasable many times and then programmable by the instructions of a program as well as by a device programmer.
A type of memory each byte of which is erasable many times and then programmable by the instructions of a program as well as by a device programmer.
EPROM
EPROM
A type of memory that is erasable many times by UV light exposure and Programmable by a device programmer.
A type of memory that is erasable many times by UV light exposure and Programmable by a device programmer.
PROM OR OTP
PROM OR OTP
A type of memory which is programmable only once by a device programmer. OTP is one time programmable memory.
A type of memory which is programmable only once by a device programmer. OTP is one time programmable memory.
RISC (Reduced Instruction Set Computer)
RISC (Reduced Instruction Set Computer)
A reduced instruction set computer that has one feature that provides a small instruction set and permits limited addressing modes for the source and destination operands in an instruction . Hardware executes each instruction in one cycle period.
A reduced instruction set computer that has one feature that provides a small instruction set and permits limited addressing modes for the source and destination operands in an instruction . Hardware executes each instruction in one cycle period.
CISC (Complicated Instruction Set Computer)
CISC ( Complicated Instruction Set Computer)
A complicated instruction set computer that has one feature that provides a big instruction set for permitting multiple addressing modes for the source and destination operands in an instruction. Hardware executes the instructions in different number of cycles. It is as per the addressing mode used in an instruction.
A complicated instruction set computer that has one feature that provides a big instruction set for permitting multiple addressing modes for the source and destination operands in an instruction. Hardware executes the instructions in different number of cycles. It is as per the addressing mode used in an instruction.
Opcode
Opcode
First byte of an instruction for the instruction decoder of the processor. It defines the operation or process to be performed on the operand(s).
First byte of an instruction for the instruction decoder of the processor. It defines the operation or process to be performed on the operand(s).
Special Function Register
Special Function Register
A register in 8051 for special functions of accumulator, data pointer, timer control, timer mode, serial buffer serial control, power down control, ports, etc.
A register in 8051 for special functions of accumulator, data pointer, timer control, timer mode, serial buffer serial control, power down control, ports, etc.
Segment Register
Segment Register
A register to point to the start of a segment for a program code or data set or string or stack.
A register to point to the start of a segment for a program code or data set or string or stack.
Index Register
Index Register
A register holding a memory address of a variable in an array, queue, table or list.
A register holding a memory address of a variable in an array, queue, table or list.
Hash Table
Hash Table
A table in which keys as stored as a first column in the table and values are stored as a second column of a table.
A table in which keys as stored as a first column in the table and values are stored as a second column of a table.
List
List
A data structure in which each object has a pointer to the next object . the first object is pointed by list-head and the last one points to a NULL pointer.
A data structure in which each object has a pointer to the next object . the first object is pointed by list-head and the last one points to a NULL pointer.
Queue
Queue
A block to memory that holds the pushed values for first in first out and last in last out data transfer.
A block to memory that holds the pushed values for first in first out and last in last out data transfer.
Stack Pointer
Stack Pointer
A register that hold an address to define the available memory address to where the processor can push the registers and variables on a stack operation and and from where they can be popped.
A register that hold an address to define the available memory address to where the processor can push the registers and variables on a stack operation and and from where they can be popped.
Program Counter
Program Counter
A processor register to hold the current instruction address to be executed after a fetch cycle on the buses.
A processor register to hold the current instruction address to be executed after a fetch cycle on the buses.
Accumulator
Accumulator
A register that provides input to an ALU and that accumulates a resulting operand from the ALU.
A register that provides input to an ALU and that accumulates a resulting operand from the ALU.
Memory Management Unit
Memory Management Unit
A unit to manage the prefetch , paging and segmentation of the memories.
A unit to manage the prefetch , paging and segmentation of the memories.
Pipelining
Pipelining
There is pipelining also in the superscalar processor. It means than its ALU circuit divides into n substages. If in its last stage the processing of a pth instruction is taking place at an instant then at the first stage processing of (p+n)th instruction is taking place. There may be multiple pipelines in a processor to process in parallel.
There is pipelining also in the superscalar processor. It means than its ALU circuit divides into n substages. If in its last stage the processing of a pth instruction is taking place at an instant then at the first stage processing of (p+n)th instruction is taking place. There may be multiple pipelines in a processor to process in parallel.
Superscalar processor
Superscalar processor
A processor with the capacity to fetch , decode and execute more than one instruction in parallel at an instant.
A processor with the capacity to fetch , decode and execute more than one instruction in parallel at an instant.
Atomic Operation
Atomic Operation
It lets a running task instruction complete operations on a shared variable in a critical region of the codes.
It lets a running task instruction complete operations on a shared variable in a critical region of the codes.
Share Data Problem
Share Data Problem
A problem in which a variable, when shared between the tasks, becomes modified by another task instruction before a running task completes operation on that variable.
A problem in which a variable, when shared between the tasks, becomes modified by another task instruction before a running task completes operation on that variable.
Branch Transfer Cache
Branch Transfer Cache
Cache to hold in advance the next set of instructions to be executed on the program branching to this set.
Cache to hold in advance the next set of instructions to be executed on the program branching to this set.
Instruction Cache
Instruction Cache
Cache to hold sequentially the instructions that have been prefetched for super scalar and pipeline based parallel execution.
Cache to hold sequentially the instructions that have been prefetched for super scalar and pipeline based parallel execution.
Instruction Queuing Unit
Instruction Queuing Unit
A unit to hold a queue of instructions and place these into the cache.
A unit to hold a queue of instructions and place these into the cache.
Prefetch Control Unit
Prefetch Control Unit
A unit to fetch instructions in advance and data in advance from the memory units.
A unit to fetch instructions in advance and data in advance from the memory units.
Instruction Decoder
Instruction Decoder
The circuit to decode the opcode of the instruction and direct he control accordingly.
The circuit to decode the opcode of the instruction and direct he control accordingly.
Control Unit
Control Unit
To control and sequence all the processing actions during an instruction execution.
To control and sequence all the processing actions during an instruction execution.
ALU (Arithmetic and Logic Unit)
ALU (Arithmetic and Logic Unit)
A unit to perform arithmetic and logic operations as per the instructions.
A unit to perform arithmetic and logic operations as per the instructions.
Arithmetic Unit Registers
Arithmetic Unit Registers
Registers hold the input and output operands and flags with ALU.
Registers hold the input and output operands and flags with ALU.
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