Maskable Interrupt
A source, which can be disable or masked.
A source, which can be disable or masked.
Monday, August 12, 2013
Non-Maskable Interrupt
Non-Maskable Interrupt
A source, which cannot be disable and is used for most needed service cases.
A source, which cannot be disable and is used for most needed service cases.
Interrupt Flag
Interrupt Flag
A register bit for a Boolean variable that sets to signal a need for executing an interrupt service routine(ISR) . It resets when a corresponding ISR starts executing.
A register bit for a Boolean variable that sets to signal a need for executing an interrupt service routine(ISR) . It resets when a corresponding ISR starts executing.
Interrupt Mask Bit
Interrupt Mask Bit
When a bit is reset (=false ) the request for the initiation of interrupt service is responded, otherwise it is not responded.
When a bit is reset (=false ) the request for the initiation of interrupt service is responded, otherwise it is not responded.
Foreground Program
Foreground Program
Foreground program is one that is executed when no interrupt call is being serviced.
Foreground program is one that is executed when no interrupt call is being serviced.
Interrupt Mechanism
Interrupt Mechanism
A mechanism for interrupt driven servicing of the devices and ports. It saves the processor waiting time, because it lets the processor process the multiple devices and virtual devices. The mechanism also sets the priorities and provides for enabling and disabling the services.
A mechanism for interrupt driven servicing of the devices and ports. It saves the processor waiting time, because it lets the processor process the multiple devices and virtual devices. The mechanism also sets the priorities and provides for enabling and disabling the services.
Interrupt Service Routine
Interrupt Service Routine(ISR)
A program that is executed on interrupt after saving necessary parameters on to the stack so that the same can be retrieved on return from the routine last instruction. An ISR is also called a device driver when it services a device interrupt.
A program that is executed on interrupt after saving necessary parameters on to the stack so that the same can be retrieved on return from the routine last instruction. An ISR is also called a device driver when it services a device interrupt.
Interrupt
Interrupt
CPU on interrupt message may initiate a further action by calling an interrupt service routine( ISR) or else it continues with the current process.
CPU on interrupt message may initiate a further action by calling an interrupt service routine( ISR) or else it continues with the current process.
Linux
Linux
An open source operating system. It has a large number of device drivers and network management functions.
An open source operating system. It has a large number of device drivers and network management functions.
Device Closing
Device Closing
Resetting the device control bits and its next time use is then possible only by opening it again.
Resetting the device control bits and its next time use is then possible only by opening it again.
Device Opening
Device Opening
Resetting the device control bits and preparing it for the use of its driver.
Resetting the device control bits and preparing it for the use of its driver.
Device Detaching (removing)
Device Detaching (removing)
Disabling the use of a device driver by the system.
Disabling the use of a device driver by the system.
Device Attaching (Adding)
Device Attaching (Adding)
Configuring a device and enabling the use of its driver.
Configuring a device and enabling the use of its driver.
Device Driver Codes
Device Driver Codes
Codes for read and write operations at the device addresses and for reading device status and initiating an interrupt.
Codes for read and write operations at the device addresses and for reading device status and initiating an interrupt.
Device Initialization Codes
Device Initialization Codes
Codes for programming the device control register of a device.
Codes for programming the device control register of a device.
IIC bus
IIC bus
A standard bus that follows a communication protocol and is used between multiple ICs. It permits a system to get data and send data to multiple compatible ICs connected on this bus.
A standard bus that follows a communication protocol and is used between multiple ICs. It permits a system to get data and send data to multiple compatible ICs connected on this bus.
Master Slave Communication
Master Slave Communication
A communication between two processors when one processor guides the transmission of the bits to a slave after receiving acknowledgement from the address slave.
A communication between two processors when one processor guides the transmission of the bits to a slave after receiving acknowledgement from the address slave.
QPSK
QPSK
Quadrature Phase Shifted Keying . It permits use of the telephone line for serial bit transmission and reception at double rate. It permits the 56 kbps modem to show a performance equivalent to 112 kbps.
Quadrature Phase Shifted Keying . It permits use of the telephone line for serial bit transmission and reception at double rate. It permits the 56 kbps modem to show a performance equivalent to 112 kbps.
PSK modulation
PSK modulation
Phase Shifted Keying modulation. The 0 and 1 logic have different phases in a high frequency signal. PSK modulation permits use of the telephone line for serial bit transmission and reception.
Phase Shifted Keying modulation. The 0 and 1 logic have different phases in a high frequency signal. PSK modulation permits use of the telephone line for serial bit transmission and reception.
FSK modulation
FSK modulation
Frequency Shifted Keying. The 0 and 1 logic states are at different frequency levels.
Example:- 0 at 1050 Hz and 1 at 1250 Hz on a telephone line. It permits telephone line for serial bit transmission and reception.
Frequency Shifted Keying. The 0 and 1 logic states are at different frequency levels.
Example:- 0 at 1050 Hz and 1 at 1250 Hz on a telephone line. It permits telephone line for serial bit transmission and reception.
SIPO
SIPO
A shift register for a Serial Parallel Input and Parallel Output. It is used for serial bits transmission in synchronous mode.
A shift register for a Serial Parallel Input and Parallel Output. It is used for serial bits transmission in synchronous mode.
PISO
PISO
A shift register for a parallel Input and Serial Output. It is used for serial bits reception in synchronous mode.
A shift register for a parallel Input and Serial Output. It is used for serial bits reception in synchronous mode.
Asynchronous Communication
Asynchronous Communication
A communication in which a constant phase difference is not maintained and the clocks that guide the transmitter and receiver are separate. Time interval between which a frame of bytes transmits is not pre-fixed and is indeterminate.
A communication in which a constant phase difference is not maintained and the clocks that guide the transmitter and receiver are separate. Time interval between which a frame of bytes transmits is not pre-fixed and is indeterminate.
Isosynchronous Communication
Isosynchronous Communication
Communication in which a constant phase difference is not maintained between frames but maintained within a frame. Clocks that guide the transmitter and receiver are not separate. Only the maximum time interval is no pre-fixed between which a frame of bytes transmits. i.e. it can be variable. Uses are for transmission on a LAN or between two processors.
Communication in which a constant phase difference is not maintained between frames but maintained within a frame. Clocks that guide the transmitter and receiver are not separate. Only the maximum time interval is no pre-fixed between which a frame of bytes transmits. i.e. it can be variable. Uses are for transmission on a LAN or between two processors.
Synchronous Communication
Synchronous Communication
Communication in which constant phase difference is maintained between the clocks that guide the transmitter and receiver. A maximum time interval is pre-fixed between which a frame of bytes transmits.
Communication in which constant phase difference is maintained between the clocks that guide the transmitter and receiver. A maximum time interval is pre-fixed between which a frame of bytes transmits.
On-Chip Ports and Devices
On-Chip Ports and Devices
The ports and devices along with the processing unit.
Example:- A micro controller
The ports and devices along with the processing unit.
Example:- A micro controller
Demultiplexing
Demultiplexing
A way to separate a multiplexed input and direct the messages to multiple channels.
A way to separate a multiplexed input and direct the messages to multiple channels.
Time Division Multiplexing
Time Division Multiplexing
A way in which in different time slots the the message from different channels can be sent.
A way in which in different time slots the the message from different channels can be sent.
Quasi Bi-directional Port
Quasi Bi-directional Port
A port with the dual advantage of using pull up circuit as per the voltage and current level required when interfacing it and using no pull up circuit for a short period sufficient to drive a LSTTL circuit.
A port with the dual advantage of using pull up circuit as per the voltage and current level required when interfacing it and using no pull up circuit for a short period sufficient to drive a LSTTL circuit.
Open Drain Output
Open Drain Output
A gate with internally a missing connection between its drain and supply. The advantage is that it pulls up circuit voltage and current levels, which are required when interfacing it. An external pull up circuit is needed when using the output.
A gate with internally a missing connection between its drain and supply. The advantage is that it pulls up circuit voltage and current levels, which are required when interfacing it. An external pull up circuit is needed when using the output.
Watchdog Timer
Watchdog Timer
An important timing device in a system that reset the system after a predefined timeout. This time may be definable within the first few clock cycles after reset.
An important timing device in a system that reset the system after a predefined timeout. This time may be definable within the first few clock cycles after reset.
Free Running Counter
Free Running Counter
A counter, which starts on power-up, which is driven by an internal clock(system clock) and which can neither be stopped nor be reset.
A counter, which starts on power-up, which is driven by an internal clock(system clock) and which can neither be stopped nor be reset.
Counter
Counter
Unit for getting the count-inputs on the occurrence of events that may be at irregular intervals.
Unit for getting the count-inputs on the occurrence of events that may be at irregular intervals.
Software Timer
Software Timer
Software Timer is a software that executes and increases or decreases a count-variable on an interrupt from a timer output or from a real-time clock interrupt. A software timer can also generate interrupt from an overflow of count-value or on finishing value of the count-variable.
Software Timer is a software that executes and increases or decreases a count-variable on an interrupt from a timer output or from a real-time clock interrupt. A software timer can also generate interrupt from an overflow of count-value or on finishing value of the count-variable.
Timer Reload
Timer Reload
State in which timer shows all bits as 0s and 1s. A reload can also be after overflow in case a timer is programmed for continuous running.
State in which timer shows all bits as 0s and 1s. A reload can also be after overflow in case a timer is programmed for continuous running.
Timer Reset
Timer Reset
A state in which the timer shows all bits as 0s and 1s . A reset can also be after over flow in case a timer is programmed for continuous running.
A state in which the timer shows all bits as 0s and 1s . A reset can also be after over flow in case a timer is programmed for continuous running.
Timer Finish
Timer Finish
A State after the timer acquired the preset count-value and stopped. An interrupt generates on finishing.
A State after the timer acquired the preset count-value and stopped. An interrupt generates on finishing.
Timer Overflow or Time-Out
Timer Overflow or Time-Out
A state in which the number of count-inputs exceeded the last acquirable value and on reaching that state, an interrupt can be generated.
A state in which the number of count-inputs exceeded the last acquirable value and on reaching that state, an interrupt can be generated.
Hardware Timer
Hardware Timer
A timer present in the system as hardware and which gets the inputs from the internal clock with the processor or system clock. A device driver program programs it like any other physical device.
A timer present in the system as hardware and which gets the inputs from the internal clock with the processor or system clock. A device driver program programs it like any other physical device.
System Clock
System Clock
A clock scaled to the processor clock and which always increments without stopping or resetting and generates interrupts at preset time intervals.
A clock scaled to the processor clock and which always increments without stopping or resetting and generates interrupts at preset time intervals.
Real Time Clock (RTC)
Real Time Clock(RTC)
A clock that continuously generates interrupts at regular intervals endlessly . An RTC interrupts ticks the other timers of the system.
A clock that continuously generates interrupts at regular intervals endlessly . An RTC interrupts ticks the other timers of the system.
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