Worst-case Latency

Worst-case Latency

Interrupt latency

Interrupt latency
A period for waiting for the service after a service demand is raised ( source status flag sets).

Stack Frame

Stack Frame
A set of registers or a memory block that stores the context for a program or ISR.

Context Switching

Context Switching 
Saving the interrupted routine (or function) context and retrieving or loading the new context of the called routine. the time take in context switching is included in the interrupt latency period.

Context

Context
Program counter, stack pointer as well as the program status work and processor registers for a foreground program or ISR or task. It can also include memory block addresses allotted to the program or routine. It can include ID. 

Status Register

Status Register
A read only register for a device to set a flag on arising of an interrupt. A user instruction can also reset a bit in it. If a device has number of sources the status register has number of flags, a distinct source for each source. When it is read by a processor instruction, the flag resets.

Interrupt Pending Register

Interrupt Pending Register 
A register to show the interrupt sources or source groups from various devices that are pending for servicing by executing the corresponding ISRs. It is a read and write register. A bit auto resets in ti when the corresponding interrupt service starts. A user instruction can also reset a bit in the register